20.Using both DAC Registers - Activate Deglitcher Circuit

DAC datasheet says when the DAC registers operating in the transparent mode the deglitcher don't work and higher glitches occurs in the output. The deglitcher circuit should be activated now by using both registers.

I developed a very simple circuit consists of one xxxx, two xxxx, one xxxx, and an xxxx, that's all.

Timing Diagram:

Timing Diagram

Schematic:

Schematic Five: Dual Monovibrator Window Generator from AN74, timing extremes for the left side diagrams, well adjustable.

Fast Digital Prototyping - faster and much more flexible than every milled or etched board.

First Measurements:

First Measurement with the new digital circuit

Today it was very hot, on such a day a fan behind the scope power supply is a must for me on a hot day.

lowest trace data bus signal
next WRX
next Load DAC
top trace Gated Settling Window

After observing this sucessfull screen I enjoyed this evening.

Full Scale Step 0V to +10V

Top Trace - Gated Settling Window
Middle Trace - DAC output (2V/DIV)
Bottom Trace - Load DAC, rising slope on first division, falling slope after 400ns tld .

Full Scale Step 0V to -10V

Top Trace - DAC output (2V/DIV)
Middle Trace - Gated Settling Window
Bottom Trace - Load DAC (5V/DIV), rising slope on first division, falling slope after 400ns tld .

Searching for DAC Glitches:

Glitch occurs - shifting the falling Load DAC edge within the gated settling window to 3.7µs shows the glitch. Let's calculate: 2.5 Divisions under 500µV/DIV at the Settle Node (1mV/DIV at the DAC Output) A 2.5mV peak Glitch under a full scale step.

Discover the System:

Negative going Full Scale Step 0V to -10V.

0V to +10V volt step
Top - Gated Settling Window, with Glitch
Next - Load DAC, falling edge within Window
Next - WRX
Bottom - data bus

Digital Electronic.

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